# --------------------global variable-----------
# clock
set OSC_FREQ 25.0
set PHY_FREQ 125.0
# sdram
set SDR_TCMS 1.5    ;# command setup time
set SDR_TCMH 1.0    ;# command hold time
set SDR_TAS 1.5     ;# address setup time
set SDR_TAH 1.0     ;# address hold time
set SDR_TDS 1.5     ;# data-in setup time
set SDR_TDH 1.0     ;# data-in hold time
set SDR_TAC 4.5     ;# access time (max TCO)
set SDR_TOH 1.5     ;# data-out hold time
set sdram_command "O_sdram_ras_n O_sdram_cas_n O_sdram_we_n"
set sdram_address "O_sdram_ba\[*\] O_sdram_addr\[*\]"
set sdram_data "IO_sdram_dq\[*\]"
set scan_out "O_oe_out O_load_out O_scan_out\[*\] O_clock_out O_data_out\[*\]"
set sdram_dqm    "O_sdram_dqm\[*\]"


# --------------------clock---------------------
# osc
create_clock \
    -period 40 \
    -name clk_in \
    [get_ports sclkin]

# gp rxc
create_clock \
    -period 8 \
    -name gp0_rxc \
    [get_ports gp0_rxc]

create_clock \
    -period 8 \
    -name gp1_rxc \
    [get_ports gp1_rxc]

derive_pll_clocks
derive_clock_uncertainty

create_generated_clock -name rgmii_p0_out_clock -source [get_pins {phy_interface|trans_io_a|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports gp0_txc]
create_generated_clock -name rgmii_p1_out_clock -source [get_pins {phy_interface|trans_io_b|oddr_1bit_txc|ALTDDIO_OUT_component|auto_generated|dataout[0]}] [get_ports gp1_txc]

# pll clock
set sclk *pll|altpll_component|auto_generated|pll1|clk\[0\]
#set sdram_clk_s *pll|altpll_component|auto_generated|pll1|clk\[1\]

create_generated_clock -name sclk_mcu -divide_by 2 -source [get_pins {sys_comm|mcu_top|clk_mcu|clk}]   [get_pins {sys_comm|mcu_top|clk_mcu|q}]

create_generated_clock -name MCU_DIV -divide_by 4 -source [get_pins {sys_comm|mcu_top|*alta_mcu_topEx01|u_mcu_ini_cfg|clk_div|clk}] [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_mcu_ini_cfg|clk_div|q}]

# --------------------false path----------------
set_false_path -to [get_ports O_sdram_clk]
set_false_path -to [get_ports O_oe_out]
set_false_path -to [get_ports O_load_out]
set_false_path -to [get_ports O_scan_out\[*\]]
set_false_path -to [get_ports O_clock_out]
set_false_path -to [get_ports O_data_out\[*\]]
set_false_path -from [get_registers *O_cfg_*]
set_false_path -from [get_registers {phy_interface|rx_clk_check_p*|clk_type*}]
set_false_path -from [get_registers {phy_interface|port_select|gp1_input*}]
set_false_path -to [get_registers sys_comm|state_ctrl|state_data*]

set_false_path -from {led_display_top:disp|rgb_pixel_save_top:rgb_pixel_save_top|pixel_crop:crop|row_num[*]}
set_false_path -to [get_registers led_display_top:disp|rgb_pixel_save_top:rgb_pixel_save_top|cxy_port_offset:port_offset|virtual_port_id[*]]

# cross clock domain
set_clock_groups \
    -asynchronous \
    -group "$sclk" \
    -group "clk_in" \
    -group "gp0_rxc" \
    -group "gp1_rxc" 

# --------------------multicycle----------------
# sdram
#set_multicycle_path \
#    -from $sdram_clk_s \
#    -to $sclk\
#    -setup 2
#set_multicycle_path \
#    -from $sdram_clk_s \
#    -to $sclk\
#    -hold 0

#set_multicycle_path \
#    -from [get_pins {bus_addr*}] \
#    -setup 2
#
#set_multicycle_path \
#    -from [get_pins {bus_addr*}] \
#    -hold 1

# --------------------input delay---------------
# sdram
#set_input_delay \
#    -clock $sdram_clk_s \
#    -max $SDR_TAC \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_data]
#set_input_delay \
#    -clock $sdram_clk_s \
#    -min $SDR_TOH \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_data]

# --------------------output delay--------------
# sdram
#set_output_delay \
#    -clock $sdram_clk_s \
#    -max $SDR_TCMS \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_command]
#set_output_delay \
#    -clock $sdram_clk_s \
#    -min -$SDR_TCMH \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_command]
#set_output_delay \
#    -clock $sdram_clk_s \
#    -max $SDR_TAS \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_address]
#set_output_delay \
#    -clock $sdram_clk_s \
#    -min -$SDR_TAH \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_address]
#set_output_delay \
#    -clock $sdram_clk_s \
#    -max $SDR_TDS \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_data]
#set_output_delay \
#    -clock $sdram_clk_s \
#    -min -$SDR_TDH \
#    -reference_pin [get_ports O_sdram_clk] \
#    [get_ports $sdram_data]

set_output_delay \
    -clock $sclk \
    -max 1.1 \
    [get_ports $scan_out]

set_output_delay \
    -clock $sclk \
    -min 1.1 \
    -add_delay \
    [get_ports $scan_out]

#####################################################################################################
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -max 3 [get_ports {gp0_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp0_rxc}] -min 1 [get_ports {gp0_rxdv}] -clock_fall -add_delay

set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -max 3 [get_ports {gp1_rxdv}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxd[*]}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxdv}] -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxd[*]}] -clock_fall -add_delay
set_input_delay -clock [get_clocks {gp1_rxc}] -min 1 [get_ports {gp1_rxdv}] -clock_fall -add_delay

set_false_path -setup -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -setup -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p0_out_clock}]
set_false_path -hold -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p0_out_clock}]

set_false_path -setup -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -setup -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -rise_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {rgmii_p1_out_clock}]
set_false_path -hold -fall_from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {rgmii_p1_out_clock}]

set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -max 9  [get_ports {gp0_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p0_out_clock}] -min -1 [get_ports {gp0_txd[*]}] -clock_fall -add_delay

set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -max 9  [get_ports {gp1_txd[*]}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txen}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txen}] -clock_fall -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txd[*]}] -add_delay
set_output_delay -clock [get_clocks {rgmii_p1_out_clock}] -min -1 [get_ports {gp1_txd[*]}] -clock_fall -add_delay

# vim: set ts=4 sw=4 et fenc=utf-8
####### mcu

set_false_path -from  [get_pins {sys_comm|frame_start_reg*}] -to sclk_mcu
set_false_path -from  [get_pins {sys_comm|com_ctrl|interrupt*}] -to sclk_mcu
set_false_path -from  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_pins {disp|sdram_ready_sr[1]*}] -to sclk_mcu
set_false_path -from  [get_pins {sys_comm|com_ctrl|com_state[4]*}] -to [get_pins  {sys_comm|com_ctrl|com_state_MCU_SEND[0]*} ]
set_false_path -from  [get_pins {sys_comm|com_ctrl|com_state[3]*}] -to [get_pins  {sys_comm|com_ctrl|com_state_MCU_RECEIVE[0]*} ]
set_false_path -from  [get_pins {sys_comm|com_ctrl|mcu_data_rec_end*}] -to [get_pins  {sys_comm|com_ctrl|mcu_data_rec_end_d[0]*} ]
set_false_path -from  [get_pins {sys_comm|com_ctrl|mcu_data_send_end*}] -to [get_pins  {sys_comm|com_ctrl|mcu_data_send_end_d[0]*} ]


#set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|display_bus|sel_ok*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -setup  2
#set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|display_bus|sel_ok*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -hold 1

set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|sel*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -setup  2
set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|sel*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -hold 1


set_multicycle_path -from  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|addr*}]    -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -setup  3 
set_multicycle_path -from  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|addr*}]    -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]   -hold 2
set_multicycle_path -from  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|wdata*}]   -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -setup  3
set_multicycle_path -from  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -through [get_nets {sys_comm|mcu_top|ahb2ram_3_inst|wdata*}]   -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -hold 2


#set_false_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_pins {sys_comm|mcu_top|ahb2ram_3_inst|hrdata*}] -to sclk_mcu

set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_pins {sys_comm|mcu_top|ahb2ram_3_inst|hready_out*}] -to sclk_mcu -setup -start  1
set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_pins {sys_comm|mcu_top|ahb2ram_3_inst|hready_out*}] -to sclk_mcu -hold  -start  1

set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_registers {sys_comm|mcu_top|ahb2ram_3_inst|hrdata*}] -to sclk_mcu -setup -start  1
set_multicycle_path -from [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -through [get_registers {sys_comm|mcu_top|ahb2ram_3_inst|hrdata*}] -to sclk_mcu -hold  -start  1

set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HADDR_EXT*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -setup -end  2
set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HADDR_EXT*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -hold  -end  1

set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HWDATA_EXT*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -setup -end  2
set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HWDATA_EXT*}]  -to  [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}]  -hold  -end  1

set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HWRITE_EXT*}] -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -setup -end   2
set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HWRITE_EXT*}] -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -hold  -end   1

set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HSEL_EXT*}]   -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -setup  -end  2
set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HSEL_EXT*}]   -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -hold   -end  1

set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HTRANS_EXT*}] -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -setup   -end 2
set_multicycle_path -from sclk_mcu -through [get_pins {sys_comm|mcu_top|alta_mcu_topEx01|u_alta_mcu|HTRANS_EXT*}] -to [get_clocks {*pll|altpll_component|auto_generated|pll1|clk[0]}] -hold    -end 1

set_false_path -from  [get_pins {disp|coe_wr|over_sr* }] -to [get_pins {disp|coe_wr|done_sr* }]
set_false_path -from  [get_pins {disp|coe_wr|req_sr* }] -to [get_pins {disp|coe_wr|start_sr* }]
set_false_path -from  [get_pins {disp|rw* }] -to [get_pins {disp|coe_wr|mux_dq_oe* }]
set_false_path -from  [get_pins {disp|sdram_addr* }] -to [get_pins {disp|coe_wr|sdram_addr* }]
set_false_path -from  [get_pins {disp|rw_len* }] -to [get_pins {disp|coe_wr|data_cnt* }]

set_false_path -from  [get_pins {sys_comm|key_cnt*}] -to sclk_mcu

#set_multicycle_path -from [get_pins {disp|coe_wr|ram|*}] -to  [get_registers {sys_comm|mcu_top|ahb2ram_3_inst|hrdata*}]   -setup  2
#set_multicycle_path -from [get_pins {disp|coe_wr|ram|*}] -to  [get_registers {sys_comm|mcu_top|ahb2ram_3_inst|hrdata*}]    -hold 1
